Conventional devices such as microprocessors and graphics processors that are used in high-performance digital systems may have varying current demands based on the processing workload. Power dissipation is a significant problem in conventional integrated circuits. A large fraction of the power dissipated in conventional digital integrated circuits is consumed in the clock network. The amount of energy that is consumed by flip-flops due to data transitions is small because the activity factor, the fraction of time the data input of the flip-flop toggles, is quite low, typically about 5-10%. In contrast, the clock input load and clock energy is an increasingly important metric to consider when determining the energy that is consumed by the latches and flip-flops in a conventional integrated circuit. Reducing the clock-switched capacitance by a given amount produces 10× the power savings compared with reducing the data-switched capacitance by the same amount.
Thus, there is a need for reducing the clock input load of a circuit and/or addressing other issues associated with the prior art.